How memory cells hold a bit

Same element, different storage structures

Silicon can support many electronic structures. A logic transistor controls a current path; a memory cell is a circuit or device arrangement that preserves distinguishable states. Designers choose structures and manufacturing steps for the job. A CPU, DRAM chip and NAND chip therefore do not become interchangeable just because each uses silicon.

Read the primary source: Micron: DRAM cells and refresh teaching material ↗ · UC Berkeley: SRAM cell research, chapter 1 ↗ · KIOXIA: floating-gate and charge-trap structures ↗

DRAM: select, sense, restore and refresh

A conventional DRAM bit cell has one access transistor and one capacitor: 1T1C. The word line controls access to a bit line. Sense-amplifier circuitry detects a small electrical difference and restores the stored state. Many cells are organised into rows, columns and banks; peripheral circuits make the small cell array usable.

Charge leaks over time, so refresh restores rows even if the program has not requested those data. Refresh is different from an application rereading a variable. Losing power removes the conditions needed to preserve ordinary DRAM contents. Exact refresh timing and operating limits belong to the chosen device specification.

Read the primary source: Micron: DRAM cells and refresh teaching material ↗ · Micron: SDRAM and DDR memory ↗

SRAM: a powered latch rather than periodic refresh

A common 6T SRAM cell uses two cross-coupled inverters plus two access transistors. Feedback maintains one of two states while power and suitable conditions remain. It does not need the DRAM-style periodic restoration of a leaking storage capacitor. It is still volatile: switch off the supply and the stored logic state is not guaranteed.

Read the primary source: UC Berkeley: SRAM cell research, chapter 1 ↗

More devices per bit typically cost area, so SRAM is useful where fast nearby storage is worth that trade-off, such as processor caches. SRAM designs also include other cell variants and substantial read/write circuitry. Registers, caches and DRAM must not all be counted as identical six-transistor bits.

Read the primary source: UC Berkeley: SRAM cell research, chapter 1 ↗

NAND: charge changes a transistor threshold

Flash stores charge in a structure that changes the transistor’s threshold behaviour. Floating-gate designs use an electrically isolated conductive storage region; charge-trap designs store charge in trapping sites in an insulating layer. Sensing compares cell behaviour with reference levels. This is a different device structure from a DRAM capacitor or an SRAM latch.

Read the primary source: KIOXIA: floating-gate and charge-trap structures ↗

A cell can encode more than one bit using more distinguishable threshold ranges: TLC encodes three bits, requiring eight possible bit patterns; QLC encodes four, requiring sixteen. The extra bits are not separate miniature SRAM latches. Narrower margins increase the importance of sensing and error management. 3D NAND builds memory-cell levels vertically; HBM instead stacks separate DRAM dies. Both use height, in different ways.

Read the primary source: KIOXIA: 3D NAND and bits per cell ↗ · Micron: HBM structure ↗

NAND is normally programmed in pages and erased in larger blocks. Its management system must account for wear and data retention. Nonvolatile means a completed stored state can persist without continuous power; it does not mean infinite retention or unlimited rewrites.

Read the primary source: Samsung: SSD components and management ↗

A RAM stick is not one DRAM die

Read the primary source: Samsung: DRAM modules and their organisation ↗

SDRAM means synchronous DRAM: its interface follows a clocked protocol. DDR families are forms of SDRAM, not a new substance replacing silicon. A module’s organisation, interface, power arrangements and supported timings must fit the memory controller. Some systems solder memory packages to the main board instead of providing a replaceable module.

Read the primary source: Micron: SDRAM and DDR memory ↗ · Samsung: DRAM modules and their organisation ↗

Worked example: count only the storage cells

Imagine an ideal 1 KiB array, with eight bits per byte. It holds 1,024 × 8 = 8,192 bits. A 6T SRAM storage-cell count is 8,192 × 6 = 49,152 transistors. A conventional 1T1C DRAM storage-cell count is 8,192 access transistors plus 8,192 capacitors. These are schematic counts, excluding addressing, sense amplifiers, tags, error protection and other peripheral circuits.

Check what survives and what the name means