Small models. Visible workings.

MODEL 1 · A CONTROLLED SWITCH

Tap the input. Follow the complementary paths.

In this ideal switch model, input 0 closes the pMOS path to the supply and opens the nMOS path to ground. Input 1 does the reverse. Both transistor gates receive the same input; the output is its logical opposite.

The 3.3 V rail is an illustrative assumption. This model uses instantaneous, ideal switches and settled 0/1 inputs. It does not calculate analog thresholds, leakage, charging current, resistance, transition behaviour or propagation delay.

Primary source: Toshiba: basic CMOS logic circuits ↗

Read how transistor control works →

MODEL 2 · EIGHT PLACES, 256 VALUES

Build a number. Keep the carry.

Each bit adds its place value when it is 1: 128, 64, 32, 16, 8, 4, 2, 1. Eight unsigned bits represent 0–255. Enter A and B or tap their bits; the full sum may need a ninth bit.

Use whole numbers from 0 to 255. Each bit button shows its place value above its current bit.

Full arithmetic sum

20

Full sum · 9-bit view

000010100

Lower 8 bits · decimal and binary

20 · 00010100

Carry out · ninth bit

0

Unsigned 8-bit overflow?

No · sum fits 0–255

13 + 7 = 20. The eight-bit result is 20, with carry 0.

Full sum = 256 × carry + lower-eight-bit result. Here “overflow” means the unsigned result exceeds 255; it is not a signed-overflow flag. The explorer shows arithmetic, not an electrical adder’s voltage or timing.

Primary source: Microsoft: the unsigned 8-bit Byte range ↗

Read the binary and place-value guide →

MODEL 3 · ONE PHASE PER TAP

Watch a tiny CPU turn 7 + 5 into 12.

This fixed, illustrative machine has an accumulator (ACC), a program counter (PC), an instruction register (IR) and three data-RAM locations. Fetch copies the instruction into IR and advances PC; decode identifies its action; execute performs it. Nothing runs automatically.

This is invented instruction notation, not an implementation of an Arm, x86 or RISC-V ISA. Every tap is a logical teaching phase, not a measured clock cycle. The fixed small integers avoid a word-width limit; the model does not simulate pipelines, caches, interrupts or electrical timing.

Predict first: after Fetch of ADD, does ACC already contain 12? No. Fetch changes IR and PC; the arithmetic occurs later, in Execute. After HALT the step button stops; Reset restores the original values.

Primary source: Arm: instruction cycle and processor components ↗

Read the instruction-cycle guide →

KEEP EXPLORING · AI LANGUAGE

From numbers in a chip to words on a screen

See how text is split into tokens, how an ID selects a vector, and how a mathematical model scores possible next tokens. Change a short training example and inspect the resulting probabilities.