CHALLENGE 1
NOT · reverse a bit
Make Y the opposite of A. A is 0 or 1; NOT maps 0 to 1 and 1 to 0.
QUANTUM SHARMA · PLS FOUNDATION · PHASE 2
Build an algorithm,
one gate at a time.
Logic Lab: eight small challenges, then a space for your own ideas. Learn how digital circuits make decisions and add numbers.
Your circuit
Loading C++ engine…TRY THE INPUTS
Build from smaller rules
0 / 32 gatesEach gate can use A, B, C (when available), a constant, or an earlier gate. Connect your final result below.
Connect the outputs
A gate is useful only when its result is connected.Every possibility
Does every row match?
KEEP A USEFUL BUILDING BLOCK
Your local design shelf
Save a checked design, load it into the free builder, or take the source with you.
Understand the eight challenges
CHALLENGE 2
AND · both conditions
Make Y equal 1 only when A and B are both 1. Try every input combination.
CHALLENGE 3
OR · either condition
Make Y equal 1 when A or B, or both, are 1. OR differs from XOR when both inputs are 1.
CHALLENGE 4
XOR · different bits
Make Y equal 1 when A and B differ. This is also the sum bit when adding two one-bit numbers.
CHALLENGE 5
NAND · invert AND
Y is 0 only when both inputs are 1. You can combine AND with NOT or use NAND directly.
CHALLENGE 6
NOR · invert OR
Y is 1 only when both inputs are 0. Test how this differs from NAND.
CHALLENGE 7
A selector · two paths
Use C as the select bit. When C is 0, Y follows A; when C is 1, Y follows B. Combine NOT, AND and OR to build the selector.
CHALLENGE 8
A half adder · two outputs
Add A and B. Y0 is the sum bit (XOR); Y1 is the carry bit (AND). For 1 + 1, carry and sum form binary 10.
Your next step: preserve a design
Use Free build to make a combinational algorithm from two or three bits. Export JSON to preserve the connections, and Verilog to describe them as hardware. An exhaustive truth table checks the selected Boolean behavior; it does not check timing, power, transistor behavior or manufacturability.
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