Making a silicon device: from wafer to tested hardware

A wafer is the beginning of device fabrication

The prepared wafer is a platform for many devices. A fab repeatedly adds material, defines patterns, removes selected material, changes local properties and measures results. This map shows purposes, not a universal manufacturing recipe: the order and repetition depend on the process and device architecture.

Source: Lam Research: deposition, etch and cleaning ↗

Three different outputs
Stage	What you have	What it does not establish
A logical design	A specified relation between inputs and outputs.	That physical transistors or wires exist.
A physical layout	Shapes and layers intended for a particular process.	That fabricated devices meet the specification.
A tested device	Manufactured hardware checked under stated conditions.	That every possible use or condition was tested.

Add a film, define a pattern, transfer it

Deposition adds a thin material film. Lithography exposes a light-sensitive resist in a pattern; development reveals selected regions. Etching can transfer that pattern into an underlying layer by removing selected material. The resist is a temporary process material, rather than the finished metal circuit. Deposition, lithography and etching do different jobs.

Source: ASML: semiconductor manufacturing steps ↗

Change electrical behaviour deliberately

Doping deliberately introduces selected atoms to control electrical properties. Ion implantation is one method; thermal processing can help activate dopants and repair implantation damage. Doping is not adding a visible wire. Contamination is unwanted, while a dopant is selected, measured and placed for a purpose.

Source: Applied Materials: modifying electrical properties ↗

Dopants can also be introduced during crystal growth. Purification and deliberate doping are compatible: what matters is control over which atoms occur where.

Source: Siltronic: crystal growth and wafer processing ↗

Connect devices and separate the conductors

Interconnects carry signals and power. Metal paths run through insulating dielectric layers; vias join wiring levels. Filling, polishing and inspection help create usable connections. A connection diagram alone does not establish resistance, capacitance or manufacturing quality.

Source: Applied Materials: interconnect materials ↗

Solar-cell processing also adds junctions, surface layers and contacts. Its architecture is different from a logic chip. A cell collects light-generated carriers; connected, protected cells form a module.

Source: US Department of Energy: solar-cell materials ↗ · US Department of Energy: PV manufacturing ↗

Test the wafer, separate die, package and test again

Wafer probing checks electrical behaviour while die are still on the wafer. Dicing separates individual die. Packaging provides suitable connections, protection and thermal support; further electrical and reliability tests check the assembled product. Flows vary, and a package can contain more than one die.

Source: Intel Foundry: wafer sort and packaging ↗ · Intel: assembly and test overview ↗

What you can build and check now

Begin with paper or the free browser activities. Arrange the material stages, explain each transformation, then build a small logic circuit and predict every binary output before running it. The activity is a model of behaviour. It does not reduce quartz, grow a wafer or fabricate the gates you draw.

Try the logic lab →

These pages teach the purpose of industrial processes. Furnace reduction, chemical purification, etching and wafer processing require engineered facilities and trained teams. For this learning path, use models and existing manufactured devices; the materials story is not a set of home chemical instructions.

Choose the next step by the evidence you need

From a model towards hardware
Path	What you learn or produce
RTL and simulation	Describe a circuit, write independent expected results and check behaviour.
FPGA	Configure already manufactured programmable logic and test it on a board.
Physical-design flow	Map and place a design, route connections and inspect process-specific reports.
Fabrication collaboration	Agree a process, accepted checks, packaging and test plan with qualified facilities.

An FPGA configures existing programmable hardware; it does not manufacture a new silicon die. For a new IC, a process design kit (PDK) supplies process-specific device and layout data. OpenROAD helps with digital physical design, but tool access does not supply every private PDK or establish foundry acceptance.

Source: AMD: programmable logic and FPGAs ↗ · SkyWater: SKY130 process design rules ↗ · OpenROAD: physical design and process support ↗

Read the RTL-to-IC guide →

Name your next deliverable

Sources and further reading

Processes differ by manufacturer and device. The explanations and exercises are original learning material; linked sources support the named industrial stages.