Inside an SSD: NAND, controller and firmware

An SSD is a system around NAND

NAND dies supply storage cells. An SSD combines those dies with a controller, firmware and electrical connections, often on a board. Packages may contain several dies, and some compact SSDs integrate their parts into one package. A RAM module can also be a board with memory chips, but it presents DRAM to a memory controller rather than managing block storage like an SSD.

Read the primary source: Samsung: SSD components and management ↗ · KIOXIA: DRAM-less SSDs and host memory buffers ↗

From a file to physical flash pages

A filesystem organises files and issues logical-block operations. The SSD controller receives storage commands and its flash translation layer (FTL) maps logical addresses to physical NAND locations. A stable logical address can therefore refer to a different physical page after an update. The host usually does not choose the exact cell where an ordinary SSD stores a file.

Read the primary source: Samsung: logical-to-physical flash mapping ↗

NAND normally needs page programming and larger-block erasure. Replacing data can write a fresh page, update the mapping and mark an old page invalid. Garbage collection later moves still-needed pages out of a block so the block can be erased and reused. Those internal moves can create more flash writes than the host requested.

Read the primary source: Samsung: SSD components and management ↗

Controller hardware and firmware work together

Read the primary source: Samsung: SSD components and management ↗

Firmware is software running in the controller’s hardware environment. It cannot remove a cell’s physical wear limits, but its placement, scheduling and recovery policies affect how the storage behaves. ECC has a defined correction capability; it does not guarantee recovery from every failed chip or every interrupted write.

On-board DRAM is optional. Some SSDs use it for working data such as mapping information; DRAM-less designs can use other resources, including a supported host memory buffer (HMB). HMB borrows host DRAM through an agreed interface. It does not mean the SSD’s persistent data now lives only in volatile RAM.

Read the primary source: KIOXIA: DRAM-less SSDs and host memory buffers ↗

NVMe, PCIe and M.2 answer different questions

NVMe specifies how host software communicates with a storage controller. It is not a kind of NAND cell. PCIe is a system interconnect commonly used by local NVMe SSDs. M.2 describes a family of module/connector arrangements, not the storage protocol by itself. The interface, physical module and actual memory technology must be identified separately.

Read the primary source: NVM Express: what the NVMe interface specifies ↗ · KIOXIA: DRAM-less SSDs and host memory buffers ↗

Likewise, an SSD’s advertised capacity is not its latency or sustained workload speed. Queueing, transfer size, internal activity and the host all matter. Nonvolatile NAND describes stored cell state, not a promise that a write still waiting in a software or volatile hardware buffer survives sudden power loss.

Worked example: one logical address moves

Use a paper SSD with logical addresses L0 and L1, and physical pages P0, P1 and P2. These names and values are invented for the example; they do not represent a real device’s page size or firmware policy.

A storage system is more than its chips

• “NAND chip = complete SSD.” A usable drive also needs control, firmware, connections and management.
• “DRAM-less means no management memory anywhere.” A controller can use different working-memory arrangements, including HMB where supported.
• “ECC prevents wear.” Error correction and distributing wear are different jobs; neither makes storage indestructible.
• “NVMe is the material holding the bits.” It specifies communication; NAND cells supply the storage medium in these examples.

Explain the layers in your own words