AGES 12+ · FREE · ENGLISH & HINDI
Your output: An instruction-by-instruction state trace with a stored answer.
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An instruction changes a machine state
A processor follows encoded instructions rather than understanding their English names. An instruction-set architecture (ISA) defines the supported operations and their meaning. A program chooses a sequence of those operations. The electrical implementation must produce the specified changes to registers, memory and control flow.
Source: MIT: designing an instruction set ↗
Our invented teaching machine has an accumulator A, addressed data RAM, a program counter PC and an instruction register IR. Registers hold state. PC selects a program entry; IR holds the fetched instruction. PC is an address holder, not the number being added. Instructions and data are shown separately.
Source: MIT: building a processor ↗
Fetch, decode, execute—and track the effects
In this model, Fetch copies the selected instruction into IR and immediately increments PC. Decode identifies its operation and operand. Execute performs the action, such as reading data, adding or writing memory. IR still holds the command being executed while PC already points to the following entry.
Source: MIT: building a processor ↗
Reading an instruction is different from executing a LOAD. Fetch obtains the command; LOAD later reads the addressed data. A read copies information without automatically erasing the source. Separate these actions in your notes instead of calling every memory access “fetch”.
Trace a four-instruction addition
Start with A = 0, PC = 0 and RAM values [7, 5, 0]. The readable teaching program is LOAD [0], ADD [1], STORE [2], HALT. Brackets mean a RAM address: ADD [1] adds the contents of location 1, which is 5, rather than adding the number 1. These names are illustrative, not an encoding for every real CPU.
| Address fetched | Instruction | PC after fetch | A after execute | RAM[2] |
|---|---|---|---|---|
| 0 | LOAD [0] | 1 | 7 | 0 |
| 1 | ADD [1] | 2 | 12 | 0 |
| 2 | STORE [2] | 3 | 12 | 12 |
| 3 | HALT | 4 | 12 | 12 |
The calculation is 7 + 5 = 12. STORE copies 12 to RAM[2]; it does not add again. HALT finishes with PC = 4, A = 12 and RAM[2] = 12. Keep “before” and “after” columns to avoid using a result before its instruction executes. This model uses small mathematical integers, without a fixed-width overflow rule.
Four instructions with three labelled phases give twelve teaching microsteps. That is a count for this model, not twelve hardware clock cycles on every processor. At each microstep, record the phase, current instruction, A and the memory change, if any.
Real processors can overlap the work
Many processors pipeline instructions: different instructions occupy different stages at the same time. This can improve throughput—the rate of completed work—without making one instruction instantaneous. Dependencies, branches and memory delays can interrupt the flow. A clock tick, one teaching microstep and a completed instruction are different units of progress.
Source: MIT: instruction pipelining ↗
The ISA describes what the program should observe; a pipeline is one way to implement it. Our loop helps you account for state changes before studying caches, parallel execution or speculation. It is a starting model, not a diagram of every processor’s internal schedule.
Predict before stepping
Put the model to work
Make a prediction, run one small check, and record the result and its limits. Explain a mismatch before changing several things at once.
Sources and further reading
Original diagrams, examples and self-check questions. Each model states its assumptions; named source lessons provide further depth.