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QUANTUM SHARMA · SILICON ATLAS

Inside a CPU: cores, instructions and caches

Follow an instruction through control, registers and an ALU, then see how caches and memory connections keep a processor supplied.

Silicon Atlas learning tree →

A CPU contains cooperating blocks

Silicon is a material. A CPU is a designed system built from devices and connections on that material. Its transistors form gates, storage circuits and larger blocks. A core is an instruction-executing engine; the CPU product can include several cores and shared support hardware.

A conceptual multicore CPU and its main memoryTwo example cores connect through an interconnect to shared cache and a memory controller. DRAM is outside the illustrated CPU boundary.Illustrative CPU boundaryCore 0Control / decodeALU + registersLocal L1 cacheCore 1Control / decodeALU + registersLocal L1 cacheShared cache exampleInterconnect: routes requests and dataMemory controllerMain-memory DRAM chips
Original conceptual diagram; connections and placement are simplified, not a chip floorplan. Scroll sideways on a narrow screen.
Read the blocks by their job
BlockWhat it does
Control and decodeInterpret instruction bits and coordinate the required operations.
ALUCompute integer arithmetic, comparisons and bitwise logic. Floating-point work may use other execution units.
RegistersKeep operands, addresses and intermediate state close to execution.
CachesKeep selected copies of instructions and data to reduce slower memory accesses.

Read the primary source: Arm: CPU components ↗ · Arm: example core and cache components ↗

From a program to an instruction

A compiler turns a program into instructions for an instruction-set architecture (ISA). The ISA defines the software-visible operations and state. Microarchitecture is the implementation: how instructions are decoded, scheduled and executed, with particular pipelines and caches. Two CPUs can implement the same ISA using different internal designs.

Read the primary source: Arm: architecture and microarchitecture ↗

For learning, trace fetch → decode → execute → write back. A real processor may overlap these stages for many instructions. Some CPUs predict branches and execute ready operations out of order, while others use simpler in-order designs. The orderly teaching sequence describes the result, not a promise that every CPU finishes one instruction per clock.

Read the primary source: Arm: CPU components ↗

Registers, SRAM cache and DRAM are different

Registers are directly named or used by instructions. A cache automatically holds selected memory copies and records which addresses they belong to. Main-memory DRAM provides a larger working space beyond the CPU. Typical caches use SRAM cells; a common SRAM bit cell uses six transistors. Extra circuits provide addressing, tags, sensing and protection.

Read the primary source: UC Berkeley: SRAM cell research, chapter 1 ↗

A cache hit finds the requested copy; a miss needs another level or main memory. L1 is commonly local to a core, while later cache organisation varies. Multiple cores may need coherence mechanisms so their cached copies obey the system’s memory rules. Cache capacity, locality and access patterns matter alongside core count.

Read the primary source: Arm: example core and cache components ↗

The core needs a surrounding system

An interconnect routes requests among cores, caches, controllers and other blocks. A memory controller schedules the commands that reach DRAM. An MMU has a different job: translating and protecting addresses. Depending on the system, controllers and connections may lie on the same die, another chiplet or another chip; the diagram is one teaching arrangement.

Read the primary source: Arm: example core and cache components ↗ · Micron: SDRAM and DDR memory ↗

A physical core is also different from a software thread. A thread is an instruction stream with its own execution context. Hardware multithreading can let one core keep more than one context, sharing some execution resources. Doubling a displayed thread count therefore does not automatically double the amount of independent hardware.

Read the primary source: Arm: CPU components ↗

Worked trace: add two stored numbers

Imagine a tiny teaching CPU with memory x = 5 and y = 7. Its symbolic instructions below are an invented learning notation, not a complete real ISA. Each row describes the intended visible state after that operation.

A four-step addition trace
OperationState after the operation
LOAD R1, [x]R1 = 5; fetch x through the memory hierarchy.
LOAD R2, [y]R2 = 7.
ADD R3, R1, R2The arithmetic unit produces R3 = 12.
STORE [z], R3The memory system receives a store of 12 to z.

Three tempting shortcuts to avoid

  • “More GHz always wins.” Clock frequency is only one input; work per instruction, memory stalls and the task also matter.
  • “Every transistor is an ALU.” Many transistors store bits or route/control data rather than performing arithmetic.
  • “A CPU is just silicon with software added.” Its physical circuits must implement the required logic, storage and interfaces before software can use them.

Read the primary source: Arm: CPU components ↗ · Arm: architecture and microarchitecture ↗

Predict, then build a small part

Connect the explanation to a project

Start with one block you can explain and test. Keep the inputs, expected outputs and limits in a notebook before expanding the design.

Build a logic block

Try the selector or half adder and check every input combination.

Open Logic Lab →

Follow the making path

See how a checked design connects to layout, process choices and real hardware.

Explore making →

Try a transistor, binary addition or CPU instruction model →