From a transistor to a CMOS inverter

A transistor controls a conducting path

A MOSFET is a field-effect transistor. Voltage on its insulated gate changes the electrical conditions that control a channel between source and drain. It is a solid-state device: no little lever moves inside. Gate, source, drain and body voltages matter; “high input always turns every transistor on” is not a general rule.

Source: MIT: MOSFETs and CMOS ↗

A controlled-switch model is useful for digital reasoning. We replace detailed current–voltage behaviour with “conducting” or “not conducting” under stated conditions. This makes a truth table easier to derive, but it cannot predict the current, temperature or speed of a manufactured transistor.

Two complementary paths make an inverter

An ideal CMOS inverter has a pMOS pull-up to the positive supply VDD and an nMOS pull-down to 0 V. Their gates share input A, and the paths meet at output Y. At valid, stable input levels, one path is on and the other is off. The result is NOT: Y is the opposite of A.

Source: MIT: inverter device models ↗

Ideal stable-state behaviour
A	pMOS	nMOS	Y
0	On	Off	1
1	Off	On	0

Original controlled-switch model at a stable input of 0. It is not a transistor cross-section or a fabrication drawing. The input controls both paths; VDD supplies the output energy.

Source: University of New Mexico: CMOS conducting paths ↗

The truth table hides electrical detail

A logic 0 or 1 corresponds to an allowed voltage range. It is not a universal promise of exactly 0 V or exactly 1 V. Specifications define valid inputs and outputs and the time allowed for an output to settle. An intermediate voltage may not be a valid logic level.

Source: MIT: the digital abstraction ↗

Real CMOS has leakage, capacitance and finite transitions. Near a switching transition both devices can conduct partly. Charging a load takes current; a slow or floating input can cause unwanted behaviour. The ideal model’s lack of a steady supply-to-ground path does not mean a real gate consumes no energy.

Source: Texas Instruments: slow and floating CMOS inputs ↗

A small charge calculation explains switching work

Capacitance describes charge change per voltage change. For an ideal fixed capacitor, ΔQ = C × ΔV. Here the variable C is capacitance in farads; the charge unit C is coulombs. The same printed letter has different roles, so always read its units.

Source: OpenStax: capacitance and charge ↗

Invent a 2 nF output load and a change from 0 V to 3 V. ΔQ = 2 nF × 3 V = 6 nC. Doubling the load to 4 nF would require 12 nC for the same change. The prefix nano means one billionth. These values illustrate arithmetic; they are not a transistor data sheet.

The input signal selects the path, while the supply provides energy to charge the output. Connecting many gate inputs adds load. To investigate an actual device, you would need its models, supply limits, load and timing conditions as well as its Boolean function.

Keep the switch model and the physics distinct

Put the model to work

Make a prediction, run one small check, and record the result and its limits. Explain a mismatch before changing several things at once.

Explore working models →Build a circuit in Logic Lab →

Sources and further reading

Original diagrams, examples and self-check questions. Each model states its assumptions; named source lessons provide further depth.