From a logic circuit to an integrated circuit

Begin with a behaviour, not a drawing

The digital abstraction models a signal as 0 or 1. Combinational outputs depend on current inputs; sequential circuits also keep state. Real voltages have ranges and delays. The binary model helps us specify a function.

Source: MIT OpenCourseWare: Computation Structures ↗

Our target is a half adder: add two one-bit inputs A and B. Sum is the low bit; Carry records a value of two. For A = 1 and B = 1, the answer is binary 10, so Sum = 0 and Carry = 1.

Build and check a half adder

Connect A and B to an XOR gate for Sum and to an AND gate for Carry. The specification is Sum = A XOR B; Carry = A AND B. Test every row before accepting the design.

The complete half-adder truth table
A	B	Sum	Carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Build the half adder in the logic lab →

Describe the same circuit in Verilog

RTL means register-transfer level. Verilog is a hardware description language: these assignments describe hardware operating concurrently. In this one-bit example, ^ means XOR and & means AND. Naming the outputs does not create a register; this module is combinational.

module half_adder(
  input wire A, B,
  output wire Sum, Carry
);
  assign Sum = A ^ B;
  assign Carry = A & B;
endmodule

A simulator and a testbench check behaviour against expected outputs. Synthesis then transforms supported RTL into a netlist of logic elements; mapping selects cells from a target library. Yosys supplies this synthesis stage. Not every simulation-language construct describes hardware that a chosen synthesis flow can build.

Source: Yosys: synthesis documentation ↗

Adding memory changes the test

A register keeps state and typically updates at a clock edge. A counter needs reset, enable and wrap-around rules. Test event sequences: current inputs alone cannot predict its output. Record the expected state after each edge.

Source: MIT OpenCourseWare: Computation Structures ↗

Give the gates physical locations and wires

A simplified digital implementation flow
Stage	Main question
Floorplan	How large is the block, and where do ports, large blocks and power structures go?
Placement	Where will the cells fit with acceptable congestion and delay?
Clock-tree synthesis	For clocked designs, how will the clock reach registers?
Routing	Which metal paths and connections join the placed cells?
Extraction and checks	What electrical effects do the wires add, and what violations remain?

Source: OpenROAD Flow Scripts: flow tutorial ↗

OpenROAD implements digital physical design. Flow controllers connect it to synthesis and other checks. It supports public and private process platforms, so open tools need not be limited to an old node. Platform data and acceptance criteria determine what a run proves.

Source: OpenROAD: tool scope and PDK support ↗

A layout needs process-specific evidence

A process design kit (PDK) supplies data tied to a manufacturing process, including layer definitions, device information and layout rules. Design-rule checking (DRC) tests geometry such as widths and spacing. Layout-versus-schematic (LVS) compares the circuit extracted from the layout with its intended connectivity.

Source: SkyWater SKY130: process design rules ↗

Static timing analysis uses the netlist, timing libraries, constraints and wire effects to check timing paths. For clocked circuits this includes setup and hold requirements. A missing constraint can leave a path unchecked; a clean-looking report needs an explanation of what was analysed.

Source: OpenSTA: static timing analysis ↗

ASAP7 is a predictive process kit, useful for research rather than a foundry fabrication commitment. For tapeout—the handoff for manufacturing—use the foundry’s accepted process data, required checks and submission rules. A truth table or exported Verilog file alone cannot establish readiness.

Source: ASAP7: predictive process kit ↗ · TSMC: EDA Alliance and tool certification ↗

Finish with a design-stage checklist

Sources and further reading

Reviewed 10 October 2026. Company examples describe the named product categories, not a complete ranking. Exercises and worked examples are original Quantum Sharma teaching material.