YOUR OUTPUT
A five-layer dependency map and a focused first project.
A few firms, or one supplier?
An oligopoly is a market where a small number of large firms supply most sales. A monopoly has one supplier in the market being described. First name the product and its substitutes: “chip design software”, “EUV production machines” and “all chips” are different markets. Concentration alone does not prove that firms have agreed to fix prices.
Source: OpenStax: oligopoly ↗
A chip is the result of many connected activities. IC means integrated circuit: electronic components and their connections made together on a chip. No single application carries out every design and manufacturing step.
Map five layers of the ecosystem
| Layer | What it supplies | Examples and evidence |
|---|---|---|
| EDA | Software to design and check electronic circuits. | Synopsys, Cadence, Siemens EDA. European Commission: semiconductor ecosystem assessment, EDA section ↗ |
| Advanced foundry processes | Factories and process platforms for manufacturing designs. | Examples: TSMC: A16 technology ↗; Intel Foundry: 18A process ↗; Samsung Foundry: company and process information ↗ |
| Lithography | Equipment that patterns selected wafer layers. | ASML: lithography products ↗; Nikon: semiconductor lithography systems ↗ |
| Compute software | Platforms for programming accelerators. | NVIDIA: CUDA programming guide ↗; AMD: ROCm documentation ↗ |
| Memory | DRAM and other memory/storage devices. | Micron, Samsung, SK hynix are important examples. Micron: 2025 annual filing, products and competition ↗ |
The advanced foundry examples are not a list of every chip factory. Memory is also several markets: DRAM and NAND flash serve different needs. Compare the same product category, process capability and date before drawing a competition conclusion.
Why EDA is difficult to replace
Synopsys, Cadence and Siemens EDA dominate the broad EDA ecosystem, but they are not its only developers. Cadence also identifies smaller providers and in-house design tools as competitors. EDA is a collection of specialised tools for simulation, synthesis, physical design and checking, rather than one universal application.
Source: European Commission: semiconductor ecosystem assessment, EDA section ↗ · Cadence: 2025 annual filing, competition ↗
Writing an algorithm is only part of a competing tool. In its review of specific Synopsys–Ansys markets, the FTC identified development expense, specialist expertise and switching costs as entry barriers. A useful replacement must also work reliably in a customer’s existing flow.
Source: FTC: Synopsys–Ansys complaint, entry barriers ↗
Foundry compatibility matters: TSMC’s EDA Alliance qualifies tools for particular design stages and process technologies. A demonstration that runs on a laptop and a tool accepted for production signoff have different evidence behind them.
A narrower example: EUV lithography
ASML is the sole commercial supplier of EUV lithography production systems. That statement is about this equipment category. ASML describes EUV as unique to it, and imec’s 2026 account identifies ASML as the only company integrating the required technologies into a machine.
Source: ASML: lithography products ↗ · ASML: EUV supplier explanation (2021) ↗ · imec: High NA EUV and ASML integration (2026) ↗
Nikon sells other lithography systems, including ArF immersion equipment. Calling all semiconductor manufacturing an ASML monopoly would hide these distinctions.
CUDA belongs to another layer
CUDA is NVIDIA’s platform and programming model for parallel work on NVIDIA GPUs. ROCm is AMD’s GPU computing software ecosystem. These are ways to use computing hardware; neither is an application that fabricates chips. A popular programming ecosystem can influence which hardware people choose, so software compatibility belongs on your dependency map too.
Source: NVIDIA: CUDA programming guide ↗ · AMD: ROCm documentation ↗
Choose a useful first contribution
Start with one narrow problem you can measure: a better truth-table explanation, a reproducible test case, a clearer timing report, or a small optimisation in an open tool. Define the users, supported inputs and success criterion. A new tool becomes credible through repeatable results on problems people actually need to solve.
Sources and further reading
- OpenStax: oligopoly ↗
- European Commission: semiconductor ecosystem assessment, EDA section ↗
- Cadence: 2025 annual filing, competition ↗
- FTC: Synopsys–Ansys complaint, entry barriers ↗
- TSMC: EDA Alliance and tool certification ↗
- TSMC: A16 technology ↗
- Intel Foundry: 18A process ↗
- Samsung Foundry: company and process information ↗
- ASML: lithography products ↗
- ASML: EUV supplier explanation (2021) ↗
- imec: High NA EUV and ASML integration (2026) ↗
- Nikon: semiconductor lithography systems ↗
- NVIDIA: CUDA programming guide ↗
- AMD: ROCm documentation ↗
- Micron: 2025 annual filing, products and competition ↗
Reviewed 10 October 2026. Company examples describe the named product categories, not a complete ranking. Exercises and worked examples are original Quantum Sharma teaching material.
